Radiation Hardened Dual D Flip-Flop w/ ASYNC CLR and OE

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AF54RHC705 Block
AF54RHC705 Block

Product Overview

The AF54RHC705 is a radiation-hardened by design dual D flip flop that is ideally suited for space, medical imaging and other applications demanding radiation tolerance and high reliability. It is fabricated in a 180 nm CMOS process utilizing proprietary radiationhardening techniques, delivering high resiliency to single-event effects (SEE) and to a total ionizing dose (TID) to 300 krad (Si).

This device is a member of the Apogee Semiconductor AF54RHC logic family operating across a voltage supply range of 1.65 V to 5.5 V.

This device consists of two D flip-flops with individual clear and clock inputs. Information at a D input is transferred to the corresponding Q output on the next positive-going edge of the clock input. Both Q and Q outputs are available for each flip-flop. The clear input  is asynchronous.

Zero-power penalty™ cold-sparing is supported, along with Class 2 ESD protection on all inputs and outputs.

A proprietary output stage and robust power-on reset (POR) circuit allow the AF54RHC705 to be cold-spared in any redundant configuration with no static power loss on any pad of the device. The redundant output stage also features a high drive capability with low static power loss.

The AF54RHC705 is dual radiation hardened D Flip Flop capable of being clocked up to 100MHz at 3.3V.

This device contains latches based on the Dual Interlocked storage Cells (DICE) that are tolerant to Single Event Upsets. The AF54RHC705 also features a triple-redundant design throughout its entire circuitry, which allows it to be immune to single-event transients (SET) without requiring additional redundant devices.

  • 1.65 VDC to 5 VDC operation
  • Inputs tolerant up to 5.5 VDC at any VCC
  • Provides logic-level down translation to VCC
  • Extended operating temperature range (-55°C to +125°C)
  • Proprietary cold-sparing capability with zero static power penalty
  • Built-in triple redundancy for enhanced reliability
  • Internal low-loss power-on reset (POR) circuitry ensures reliable power up and power down responses during hot plug and cold sparing operations
  • Class 2 ESD protection (4000 V HBM, 500 V CDM)
  • TID resilience of 300 krad (Si)
  • SEL resilient up to LET 80 MeV-cm2/mg
  • MEO/GEO Satellites
  • Deep Space Exploration
  • Nuclear Imaging
  • Counters
  • Shift Registers
  • Input Synchronization


Part NumberPedigreePackageLead FinishTID
[krad (Si)]
AF54RHC705ELT-REvaluationTSSOP14SnPb30080Contact UsContact Us
AF54RHC705CLT-RFlight Grade 'C'TSSOP14SnPb30080Contact UsContact Us
AF54RHC705BLT-RFlight Grade 'B'TSSOP14SnPb30080Contact UsContact Us
AF54RHC705ALT-RFlight Grade 'A'TSSOP14SnPb30080Contact UsContact Us

Development Boards

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