Dual D Flip-Flop with Asynchronous Clear
The AP54RHC705 is a radiation-hardened by design Dual D Flip Flop that is ideally suited for space, medical imaging, high-energy physics and other applications demanding radiation tolerance and high reliability. It is fabricated in a 180 nm CMOS process utilizing proprietary radiation-hardening techniques, delivering high resiliency to single-event effects (SEE) and to a total ionizing dose (TID) up to 30 krad (Si).
This device is a member of the Apogee Semiconductor AP54RHC logic family operating across a voltage supply range of 1.65 V to 5.5 V.
Zero-power penalty™ cold-sparing is supported, along with Class 2 ESD protection on all inputs and outputs. A proprietary output stage and robust power-on reset (POR) circuit allow the AP54RHC705 to be cold-spared in any redundant configuration with no static power loss on any pad of the device. The redundant output stage also features a high drive capability with low static power loss.
The AP54RHC705 also features a triple-redundant design throughout its entire circuitry, which allows it to be immune to single-event transients (SET) without requiring additional redundant devices.
- 1.65 VDC to 5 VDC operation
- Inputs tolerant up to 5.5 VDC at any VCC
- Provides logic-level down translation to VCC
- Extended operating temperature range (-55°C to +125°C)
- Proprietary cold-sparing capability with zero static power penalty
- Built-in triple redundancy for enhanced reliability
- Internal low-loss power-on reset (POR) circuitry ensures reliable power up and power down responses during hot plug and cold sparing operations
- Class 2 ESD protection (4000 V HBM, 500 V CDM)
- TID resilience of 30 krad (Si) or 300 krad (Si)
- SEL resilient up to LET 80 MeV-cm2/mg
- LEO Constellations
- Small satellites
- Medical Imaging